The present invention relates to semiconductor devices having accurately dimensioned interconnection patterns. The present invention is particularly applicable to ultra large-scale integrated (ULSI) circuit devices having features in the deep sub-micron regime.
As integrated circuit geometries continue to plunge into the deep sub-micron regime, the requirements for dimensional accuracy becomes increasingly difficult to satisfy. Integration technology is considered one of the most demanding aspects of fabricating ULSI devices. Demands for ULSI semiconductor wiring require increasingly denser arrays with minimal spacings between narrower conductive lines. Implementation becomes problematic in manufacturing semiconductor devices having a design rule of about 0.12 micron and under.
Conventional semiconductor devices comprise a semiconductor substrate, typically doped monocrystalline silicon, and a plurality of sequentially formed interlayer dielectrics and conductive patterns. An integrated circuit is formed containing a plurality of conductive patterns comprising conductive lines separated by interwiring spacings, and a plurality of interconnect lines, such as bus lines, bit lines, word lines and logic interconnect lines. Typically, the conductive patterns on different levels, i.e., upper and lower levels, are electrically connected by a conductive plug filling a via hole, while a conductive plug filling a contact hole establishes electrical contact with an active region on a semiconductor substrate, such as a source/drain region. Conductive lines are formed in trenches which typically extend substantially horizontal with respect to the semiconductor substrate. Semiconductor xe2x80x9cchipsxe2x80x9d comprising five or more levels of metallization are becoming more prevalent as feature sizes shrink into the deep sub-micron regime.
It A conductive plug filling a via hole is typically formed by depositing an interlayer dielectric (ILD) on a conductive layer comprising at least one conductive feature, forming an opening through the ILD by conventional photolithographic and etching techniques, and filling the opening with a conductive material. Excess conductive material or the overburden on the surface of the ILD is typically removed by chemical-mechanical polishing (CMP). One such method is known as damascene and basically involves forming an opening in the ILD and filling the opening with a metal. Dual damascene techniques involve forming an opening comprising a lower contact hole or via hole section in communication with an upper trench section, which opening is filled with a conductive material, typically a metal, to simultaneously form a conductive plug in electrical contact with a conductive line.
Copper (Cu) and Cu alloys have received considerable attention as alternative metallurgy to aluminum (Al) in interconnect metallizations. Cu is relatively inexpensive, easy to process, and has a lower resistively than Al. In addition, Cu has improved electrical properties vis-à-vis tungsten (W), making Cu a desirable metal for use as a conductive plug as well as conductive wiring. However, due to Cu diffusion through dielectric materials, such as silicon dioxide, Cu interconnect structures must be encapsulated by a diffusion barrier layer. Typical diffusion barrier materials include tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), titanium-tungsten (TiW), Tungsten (W), tungsten nitride (WN), Ti-TiN, titanium silicon nitride (TiSiN), tungsten silicon nitride (WSiN), tantalum silicon nitride (TaSiN) and silicon nitride for encapsulating Cu. The use of such barrier materials to encapsulate Cu is not limited to the interface between Cu and the ILD, but includes interfaces with other metals as well.
Cu interconnect technology, by and large, has been implemented employing damascene techniques, wherein a first dielectric layer, such as a silicon oxide layer, e.g., derived from tetraethyl orthosilicate (TEOS) or silane, or a low dielectric constant material, i.e., a material having a dielectric constant of no greater than about 3.9 (with a dielectric constant of 1 representing a vacuum), is formed lover an underlying metal level having a capping layer thereon, e.g., a Cu or Cu alloy features with a silicon nitride capping layer. A barrier layer and optional seedlayer are then deposited, followed by Cu deposition, as by electrodeposition or electroless deposition.
In implementing dual damascene techniques, particularly via first-trench last dual damascene processing, on a silicon nitride capped lower Cu or Cu alloy feature, it was found difficult to form the overlying trench with a high degree of dimensional accuracy. It was also found that such dual damascene processing required a large number of manipulative steps, thereby reducing efficiency and increasing manufacturing costs.
In implementing conventional damascene techniques, for example as schematically illustrated in FIGS. 1 through 3, an underlying metal feature 16, e.g., a Cu or Cu alloy line, is formed in an underlying dielectric layer 10 with a silicon nitride capping layer 11 formed thereon. Silicon nitride capping layer 11 does not exhibit favorable anti-reflective properties to enable subsequent photolithographic processing with high dimensional accuracy, particularly as dimensions plunge into the deep sub-micron regime. Silicon oxynitride is not a viable candidate for capping layer 11, since silicon oxynitride would not effectively prevent Cu diffusion.
As further illustrated in FIG. 1, a first dielectric layer 12 is formed over underlying dielectric layer 10 on capping layer 11, a middle etch stop layer 13, such as silicon oxynitride, is formed on dielectric layer 12, and a second dielectric layer 14 is formed on middle etch stop layer 13. A photoresist mask (not shown) is then formed on second dielectric layer 14 and anisotropic etching is conducted to form via hole 15 extending through second dielectric layer 14, middle etch stop layer 13 and first dielectric layer 12. A thin organic bottom anti-reflective coating (BARC) 17 is then optionally formed at the bottom of via hole 15.
A second photoresist mask 18 is then formed over second dielectric layer 14. Second photoresist mask 18 typically has a thickness xe2x80x9cTxe2x80x9d of about 4,000 xc3x85 to about 6,000 xc3x85 and contains an opening xe2x80x9cWxe2x80x9d substantially corresponding to the width of the trench to be formed in second dielectric layer 14.
Adverting to FIG. 3, anisotropic etching is then conducted to form a trench 20 in second dielectric layer 14 stopping on middle etch stop layer 13 which is selected for its high etch selectivity with respect to second dielectric layer 14. Optional organic BARC 17 is removed during or subsequent to trench formation. In implementing Cu or Cu alloy metallization, a barrier layer 30, such as Ta or TaN, is deposited to line the dual damascene opening comprising upper trench 20 communicating with lower via hole 12, and a seedlayer 31 deposited thereon. A Cu or Cu alloy is then deposited by electrodeposition or electroless deposition to fill the dual damascene opening. The over-burden is then removed by chemical-mechanical polishing (CMP) such that the upper surface 24 of the filled damascene opening is substantially coplanar with the upper surface 25 of the second dielectric layer 14. A capping layer 26, such as silicon nitride, is then deposited to encapsulate the dual damascene structure comprising Cu or Cu alloy line 22 connected to Cu or Cu alloy via 23 which is electrically connected to underlying Cu or Cu alloy line 16.
As miniaturization proceeds apace with an attendant shrinkage in the size of metal lines, e.g., metal lines having a width of about 0.3 micron and under, e.g., about 0.2 micron and under, it becomes increasingly difficult to maintain the requisite dimensional accuracy of the metal lines, particularly when implementing dual damascene techniques. In addition, the implementation of dual damascene techniques in Cu or Cu metallization involves a large number of processing steps which becomes a competitive factor. Accordingly, there exists a need for efficient interconnection methodology enabling the formation of metal features, such as metal lines, with high dimensional accuracy. There exists a particular need for Cu or Cu alloy dual damascene methodology enabling the formation of dual damascene interconnection structures comprising accurately dimensional lines having a width of about 0.3 micron and under, e.g., about 0.2 micron and under.
An advantage of the present invention is a semiconductor device comprising an interconnection pattern with high dimensional accuracy.
Another advantage of the present invention is an efficient method of manufacturing a semiconductor device comprising an interconnection pattern with accurately dimensioned metal lines.
Additional advantages and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned by practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method of manufacturing a semiconductor device, the method comprising: forming a silicon carbide capping layer/bottom anti-reflective coating (BARC) on a metal feature; forming a dielectric layer on the silicon carbide capping layer/BARC; forming a via hole defined by exposed side surfaces of the dielectric layer and a bottom terminating on the silicon carbide capping layer/BARC; and forming a trench in an upper portion of the dielectric layer in communication with the via hole.
Embodiments of the present invention comprise forming the silicon carbide capping layer/BARC at a thickness of about 300 xc3x85 to about 1,000 xc3x85 and having an extinction coefficient (k) of about xe2x88x920.2 to about xe2x88x920.5 on an underlying Cu or Cu alloy feature, e.g., a Cu or Cu alloy line, depositing an ILD containing a dielectric material with a dielectric constant no greater than about 3.9 at a thickness of about 2,000 xc3x85 to about 12,000 xc3x85, optionally forming an organic BARC on the exposed silicon carbide capping layer/BARC at the bottom of the via hole, conducting a timed etched to form the trench in the ILD at a depth of about 300 xc3x85 to about 800 xc3x85, and then sputter etching to remove the exposed silicon carbide capping layer/BARC at the bottom of the via hole, wherein removed silicon carbide redeposits on and forms a thin film of silicon carbide on the exposed side surfaces of the ILD to protect the ILD from copper diffusion. Embodiments of the present invention further include filling the dual damascene opening with Cu or a Cu alloy by electroless plating or electroless deposition, conducting CMP and Then forming a capping layer encapsulating the dual damascene structure. Advantageously, the capping layer can also comprise silicon carbide having an extinction coefficient of about xe2x88x920.2 to about xe2x88x920.5 to enable the formation of subsequent metal levels comprising features exhibiting high dimensional accuracy.
Another aspect of the present invention is a semiconductor device comprising: a dielectric layer containing a lower metal feature; a silicon carbide capping layer/BARC on an upper surface of the dielectric layer; an ILD on the silicon carbide capping layer/BARC; and a dual damascene structure formed in the ILD, the dual damascene structure comprising an upper metal line connected to a metal via in electrical contact with the lower metal feature.
Embodiments of the present invention comprise a semiconductor device wherein the lower metal feature, upper metal line and metal via comprise Cu or Cu alloy, the silicon carbide capping layer has an extinction coefficient (k) of about xe2x88x920.2 to about xe2x88x920.5, and a silicon carbide capping layer encapsulating the dual damascene structure, wherein the encapsulating silicon carbide layer has an extinction coefficient (k) of about xe2x88x920.2 to about xe2x88x920.5. As employed throughout this disclosure, the symbol Cu is intended to encompass high purity elemental copper as well as copper-based alloys, such as copper alloys containing minor amounts of tin, zinc, manganese, titanium, germanium, zirconium, strontium, palladium, magnesium, chromium and tantalum.
Additional advantages of the present invention will become readily apparent to those having ordinary skill in the art from the following detailed description, wherein embodiments of the present invention are described simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present invention. Accordingly, the drawings and descriptions are to be regarded as illustrative in nature and not as restrictive.